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ICACHE

CPU cache

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from

MicroSPARC

(millions) Die size (mm²) IO Pins Power (W) Voltage (V) L1 Dcache (k) L1 Icache (k) L2 Cache (k) L3 Cache (k) microSPARC I (Tsunami) TI TMS390S10 / TMX390S10

Tremont (microarchitecture)

clustered 6-wide out-of-order front-end fetch and decode pipeline. Banked ICache with dual 16B reads. Two 3-wide decode clusters enabling up to 6 instructions

Intel i960

5 V Parts Model Number Core Frequency Bus Frequency Multiplier iCache dCache Voltage Socket 80960MC 20,25 MHz 20,25 MHz 1.0x 0.5 KByte none 5.0 V PGA-132

Sysinfo

68000 7MHz 0.98 X EClock Hz 715909 B2000 68000 7MHz 0.74 X Ramsey rev N/A ICache N/A A1200 EC020 14MHz 0.42 XX Gary rev N/A DCache N/A A2500 68020 14MHz

DEC Alpha

Transistors [millions] Die size [mm2] IO pins Power [W] Voltage Dcache [KB] Icache [KB] Scache Bcache ISA EV4 21064 1992 100–200 0.75 1.68 234 290 30 3.3 8

SPARC

(millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB) SPARC MB86900 Fujitsu 14.28–33 V7 1986

Criticism of Linux

that I envisioned 15 years ago ... The kernel is huge and bloated, and our icache footprint is scary. I mean, there is no question about that. And whenever

Motorola 68060

32 bit Instruction set CISC Cache 8 KB DCache (4-way associative) 8 KB ICache (4-way associative) 96 byte FIFO Instruction Buffer 256 Entry Branch Cache

PA-RISC

Process [μm] Transistors [millions] Die size [mm2] Power [W] Dcache [KB] Icache [KB] L2 cache [MB] ISA Notes TS-1 ? 1986 8 ? ? — — ? 64 64 — 1.0 CS-1 ?